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-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:55:58 09/23/2011 
-- Design Name: 
-- Module Name:    multopblk - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity multopblk is
    Port ( mk1 : in  STD_LOGIC;
           mk : in  STD_LOGIC;
           q0 : in  STD_LOGIC;
           q1 : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           cout : out  STD_LOGIC;
           OP : out  STD_LOGIC);
end multopblk;

architecture Behavioral of multopblk is

begin
OP<= (mk1 and q0) xor (mk and q1) xor cin;
cout<=((mk1 and q0) and (mk and q1))xor(cin and((mk1 and q0) xor (mk and q1)));


end Behavioral;

